This position is for our client which is into IT Industry
Senior SoC Performance Verification Engineer
Today's complex SOCs have demanding performance goals. Meeting these goals is critical for success of these parts. The performance verification team is responsible to qualify that the design architecture and implementation meets these goals with detailed metrics analysis and cross correlation across model, RTL, emulation.
The job expectations include the following:
?The candidate is expected to develop in depth understanding of chip architecture and define/ develop performance verification scenarios to test design/ architecture and report bottlenecks/ optimization opportunities. The test cases should cover system scenarios/ benchmarks which stress target path/ feature as well as subsystem analysis.
?The reference metrics to qualify the results needs to be synthesized based on references from system architecture team, software team, IP team, industry standards or defined based on abstract use case descriptions available as part of design requirements.
?Establish performance correlation with different levels of abstraction ? TLM model, RTL and emulation. Also, work with silicon validation to support/ extend the correlation to final silicon and focus analysis based on customer feedback/ quality incident/ special use case requirements.
Some of the challenging responsibilities include:
?Designing / developing performance tests (including performance benchmarks) with deep understanding of Use Case and hardware systems
?Arrive at actionable list of improvements in design centred around ARM/Network on Chip/Cache coherent Interconnects/DDR Controllers/Memory Subsystems
?Working with cross domains - IP owners, Systems and Core design teams to achieve performance verification objectives and / or close performance verification loop with SW deliverables
?Analyzing big data space and correlate across metrics to identify design/ architecture issues. This usually involves building on more targeted scenarios with the goal to generate adequate data to understand design architecture behavior under different traffic profiles.
?Good domain knowledge expertise on ARM interconnects / Network On Chip including Cache Coherence with understanding of performance features
?Understanding of memory subsystems, caches, DDR controllers, Flash memory controller architectures.
?Ability to comprehend system level use cases, h/w s/w interactions and develop mathematical representation/ model use case workload with task graphs, generic traffic, RTL or software proof points.
?Strong Programming skills in C/C++/ Python or other languages to enable data analytics
?Experience with HDLs like Verilog, System Verilog, SOC RTL verification, UVM methodology to execute, analyze and debug performance test cases.
?Domain knowledge in at least some of the areas like Graphics/Multimedia/Networking IPs like PCIe, MIPI, GPU, H.264, Ethernet, USB, ITU T.656, DSP, Image/Computer Vision, RADAR processing, Digital Signal processing.
?Experience with TLM, SystemC or modeling tools like Platform Architect etc. is an added advantage
?User level experience to execute, analyze and debug test cases on emulation platform would be an added advantage.