Hiring FPGA Design Engineer (2 to 4 Year Experience)
Develops RTL code to meet the requirements. Verifying module level code using test benches, generating binaries, and validating on hardware. Debugs the code on hardware using innovative approaches.
Good understanding of fundamentals: FPGA architecture, Logic Design concepts
Strong RTL Programming skills in VHDL, Verilog
Good understanding of and work experience in Altera / Xilinx
Good understanding of the following concepts: Multi Clock designs, Asynchronous interface,
Good experience in standard Protocols: AXI / AHB / Avalon Interface (Altera)
Familiar with Tools: Quartus Prime / Xilinx ISE / Xilinx Vivado
Experience in Static Timing Analysis
Strong focus on perfection and quality conscious development.
Design and develop reusable IP components.
Follow best practices in RTL Coding.
Excellent debugging and performance optimization skills.