Hiring FPGA Verification Engineer (2 to 4 Year Experience)
Develops functional & performance validation tests to verify system to meet design requirements. Creates test plans for RTL validation, defining and running system simulation models, and finding and implementing corrective measures for failing RTL tests. Analyzes and uses results to modify testing.
Good understanding of fundamentals: Logic Design, Functional & Performance Verification
Strong RTL Programming skills in System Verilog; good understanding of other programming languages like Verilog / VHDL
Sound understanding of functional verification fundamentals encompassing state machine verification, functional test strategies, directed and stress test generation, verification infrastructures and verification and/or debug flows
Good knowledge on functional and code coverage Perform the overall verification methodology using HVLs like system Verilog, OVM, UVM
Experience in complex protocol verifications