Roles & Responsibilities :
·
The
individual will be responsible for complete ownership of full chip Synthesis
environment for low power, high performance designs, development-debug of
interface and core side constraints, clock tree analysis and assisting full
chip timing convergence and timing closure.
·
Additional
responsibilities include proactively working with the DFT teams and EDA vendors
to assess best in class tools / capability and benchmark them to drive
compelling adoption arguments.
·
He /
She will also drive IP integration strategies that ensure quality ASICs and
avoid schedule surprises.