Roles & Responsibilities :

·         UG/PG with 3-8 years of relevant work experience and strong understanding of DFT concepts

·         Strong hands on Experience using industry standard EDA Tools

·         Experience with logic simulators from one or more EDA vendors

·         Experience on Mentor Tessent tools and Cadence Modus Test tools

·         Experience with RTL lint tools like Synopsys Spyglass

·         Experience in scan insertion, coverage analysis and debugging skills on faults coverage enhancement is required

·         Exposure to RTL2GDS flow and tasks such as synthesis and scan insertion, STA and IR drop

·         Experience in post silicon validation, ATE debug and support is desired

·         Good understanding of Logic design, RTL implementation & verification, logic synthesis, Logic Equivalent Checking & Static Timing Analysis is a plus

·         Experience on multiple complex chips at different technologies like 14nm/10/7nm etc

·         Participate in driving new DFT methodology and solutions to improve quality, reliability and in-system test and debug capability

·         Programming in Perl, Tcl or other scripting languages is a plus